Wait state mechanism for a high speed bus which allows the bus to continue running a preset number of cycles after a bus wait is requested
US5339440A · kind A · utility
3Cited by
16References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 1992 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Aug 21, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.