High speed sample and hold circuit and radio constructed therewith
US5339459A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1992 |
| Grant date | Aug 16, 1994 |
| Priority date | — |
| Expiry date | Dec 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/26
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit is formed within an integrated circuit and has a small, substantially linear hold capacitance. The circuit includes a sampling switch, a hold capacitor, and a buffer amplifier. The buffer amplifier includes a common drain FET and a constant current source FET. The common drain FET provides an input which couples to the hold capacitor. The constant current FET isolates the source of the common drain FET from ground. The sample and hold circuit may be used as a wide bandwidth mixer. In a radio application, a pulse generator provides a stream of pulses in which the sampling rate times an integer number equals the RF frequency minus the IF frequency. The width of the sampling pulse is less than the period of an RF signal. In an oscillator application, the sample and hold circuit operates as a mixer in a frequency multiplying phase locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.