High performance output buffer with reduced ground bounce
US5341040A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1993 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Feb 9, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides circuitry for compensating the slew rate of an output buffer so as to reduce the magnitude of the variation in slew rate and ground bounce due to temperature and processing variations. The circuitry includes structure at the gate of each transistor that supplies or sinks current to charge or discharge capacitance at the output buffer output that slows down the turn on of the output transistors as temperature or process shifts in a way that would tend to increase the current carrying capability of the output transistor. The structure includes a transmission gate having its source connected to the gate of the output transistor, its drain connected to a capacitor, and its gate connected such that it is conducting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.