Flexible configuration logic array block for programmable logic devices
US5341044A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1993 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Apr 19, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.