Clock invert and select circuit
US5341048A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1992 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Nov 25, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for selectively inverting a clock signal. Clock (CLK) and inverted clock (NCLK) signals are generated. A control signal (RCTL) and inverted control signal (NRCTL) operate the clock invert circuit (201). First (C1) and second (C2) output lines are coupled to both of the clock and inverted clock signals, but are selectively connected to one of such signals by way of the control and inverted control signals. According to a preferred aspect of the invention, the control signals are generated with an SRAM bit (207). The clock and inverted clock signals are used in, for example, a programmable logic device such as with a flip-flop (205) clock input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.