Job configuration for semiconductor manufacturing
US5341302A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1992 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Apr 23, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q10/06
- WIPO fieldIT methods for management
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for configuring semiconductor jobs to achieve a desired level of set serviceability, in either probability or expectation, using a minimal number of wafers. The configuration problem is formulated as a mathematical optimization, where the serviceability level and yield losses, at chip, wafer and job levels, are explicitly considered. The problem is then reformulated by replacing the mathematically intractable service level constraints with tractable lower bounds. The reformulated mathematical optimization is efficiently solved using marginal allocation, giving good, feasible solutions to the original configuration program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.