Wiring layout design method and system for integrated circuits
US5341310A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1991 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Dec 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wiring layout design method and system providing efficient routing of wiring paths between multiple function blocks in an integrated circuit is disclosed. Associated with the function blocks are logic service terminals (LSTs) aligned on-grid relative to the global wiring layout. The technique utilizes a locator designating a desired contact point for each on-grid LST to be connected. The contact point designation is made without restriction relative to the predetermined grid pattern of the logic service terminals. Subsequent use of a conventional global wiring layout program to generate a layout of connections between LSTs, a reformatting program connects each wired logic service terminal to its desired contact point on the associated function block using the corresponding locator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.