Method for generating a test to detect differences between integrated circuits
US5341314A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1992 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Sep 2, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test (i.e., a set of test vectors) for differentiating between two different integrated circuit versions (12,14) is established by first modeling the circuits in a simulated system such that: (a) the corresponding inputs of the circuits are coupled in parallel, (b) the corresponding outputs of the circuits are exclusively OR'd by a separate one of a plurality of exclusive OR gates (18.sub.1,18.sub.2,18.sub.3 . . . 18.sub.m), and (c) the outputs of the exclusive OR gates are OR'd by an OR gate (20). Thereafter, a set of test vectors is generated, using conventional techniques, such that the vectors, when input to the different-version integrated circuits, cause a predetermined logic level signal to the OR gate (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.