Bit level pipeline divide circuit and method therefor

US5341322A · kind A · utility

Assignee

• Teknekron Communications Systems, Inc. · US

Inventors

• Gerhard Fettweis · Dresden, DE
• Herbert Dawid · Herzogenrath, DE

Key dates

• Filing date: May 11, 1992
• Grant date: Aug 23, 1994
• Expiry date: May 11, 2012

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2207/3884
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A divide circuit having bit level pipeline capability uses an array of bit level carry save adders with each carry save adder having a corresponding absolute value bit level circuit. In one or two's complement notation, the carry save adders subtract the binary values supplied thereto and generates an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary number supplied thereto. The circuit performs division in accordance with the following algorithm: Q.sub.w 1 I=W-1 to 0 N=N-D S=Signbit (N) Q.sub.I =S (EXOR) Q.sub.I+1 N=.vertline.N.vertline. D=D/2 END A recursive divide circuit employing an array of carry save adders and absolute value bit level circuits achieves full pipeline bit level capability.