Method for wear leveling in a flash EEPROM memory
US5341339A · kind A · utility
346Cited by
13References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 1993 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Nov 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a process for cleaning up a flash EEPROM memory array separated into blocks which may be separately erased, in which process all valid data is first written to other blocks of the array, and then the block is erased, the improvement including the step of determining a block to clean up based on a comparison of the number of invalid sectors each block includes and the number of switching operations which each block has undergone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.