Address mark triggered read/write head buffer
US5341479A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1991 |
| Grant date | Aug 23, 1994 |
| Priority date | — |
| Expiry date | Oct 16, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/10916
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The address mark triggered read/write head buffer provides a buffer memory for each read/write head in the rotating media data storage system that stores the entire track of data that includes the requested data record. Thus, the address mark triggered read/write head buffer retrieves the requested data record independent of the control module so that a seek request from the processor can be handled as soon as the beginning of the next data record stored on the track is positioned below the associated read/write head. The entire track is thereby staged faster on the average than the time to retrieve the requested data record. The address mark triggered read/write head buffer includes an address mark detection circuit to identify the beginning of the data field in each data record. The address mark is a predetermined data pattern of n bits that is written on the track a predetermined distance in advance of the data field of the data record. The address mark detection circuit compares the n data bits most recently read from the track with this predetermined data pattern of n bits as stored in memory. Once a match is detected, the buffer is enabled to store the next data record writte…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.