Frequency locked loop
US5343169A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 1993 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Mar 25, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency locked loop includes a phase comparator receiving first and second periodic signals and having a first output providing pulses if the first signal is in phase advance with respect to the second signal and a second output providing pulses in the opposite case; an oscillator providing the second signal; a counter, the state of which determines the frequency of the oscillator, having an incrementation input and a decrementation input; and a sampling circuit for transmitting each Nth of the pulses either to the incrementation input if the pulse occurs at one of the first and second outputs of the comparator, or to the decrementation input if the pulse occurs at the other of the first and second outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.