Circuit for improving carrier rejection in a balanced modulator
US5343171A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1992 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Sep 28, 2012 |
Classification
- Technology area (CPC F)Mechanical Engineering; Lighting; Heating
- CPC primaryF02B2075/027
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A carrier rejection circuit for improving carrier rejection in a balanced modulator includes balun transformers, connected to the carrier signal port and the modulated signal port, which reduces parasitic carrier leakage by reducing the average voltages at the ports, offset adjustment circuitry, connected to the modulating signal port, which applies an adjustable offset voltage to the modulating signal to reduce in-phase parasitic carrier leakage and carrier leakage caused by offset voltage at the modulating port, and a reactance network, connected between the carrier signal port and the modulated signal port, for reducing quadrature-phase parasitic carrier leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.