Image coding apparatus
US5343256A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1992 |
| Grant date | Aug 30, 1994 |
| Priority date | — |
| Expiry date | Apr 24, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/587
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image coding apparatus for sequentially coding an input image signal that is supplied at a predetermined frame rate at a rate that is independent of such a frame rate, thereby obtaining a coding image signal for transmission from which frames are thinned out. The apparatus comprises: a frame memory having a recording area corresponding to one frame of the input image signal to store the input image signal; a write address generator to sequentially generate write addresses in the frame memory in correspondence to the input image signal; a coder to execute a coding process by using the signal which is read out from the frame memory; a read address generator to sequentially generate read addresses in the frame memory in response to a frame change request which is generated from the coder; and a write limiter for comparing the write address and the read address, for stopping the subsequent writing operation of the frames written in the frame memory when the write address approaches the read address, and for restarting the writing operation from the head of the next frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.