Delay matching for video data during expansion and compression
US5345272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1992 |
| Grant date | Sep 6, 1994 |
| Priority date | — |
| Expiry date | Nov 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/641
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory. A second line memory in a parallel signal path processes video chrominance data from the video signal. A control circuit generates respective timing signals for writing data into each of the first and second memories and for reading data from each of first and second the line memories. A timing delay circuit for the control circuit, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During the expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values. The line memories are first in first out (FIFO) devices having independently enabled write and read ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.