Semiconductor memory device
US5345420A · kind A · utility
1Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 1993 |
| Grant date | Sep 6, 1994 |
| Priority date | — |
| Expiry date | May 25, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device for reading data from a selected memory cell. The memory cells are arranged in an array. First bit lines and word lines, coupled to the memory cells, are arranged in a matrix. The word lines select the selected cell. An amplification circuit amplifies the current passing through the selected memory cell and is coupled to the first bit line. A second bit line is coupled to the amplification circuit and carries the amplified current. A sensing circuit coupled to the second bit line senses the current on the second bit line. As a result, the current passing through the selected memory cell is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.