Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled
US5345564A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1992 |
| Grant date | Sep 6, 1994 |
| Priority date | — |
| Expiry date | Mar 31, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral integrated electronic circuit of the type having an interface for serially transferring data between it and a central processing unit ("CPU") in a computer system that employs a number of such peripheral circuits that are selectively rendered operable by the CPU, one at a time. The peripherals each include an interface that receives an initial data word from the CPU that identifies the peripheral circuit with which data is to be transferred by the CPU. Rather than all such peripherals in a computer system being powered-up in order to have their processors determine individually under software control whether they have been identified by the CPU, only a small hardwired interface circuit is so enabled. Once this interface circuit determines that the CPU desires to conduct data transfer with it, the main portion of the circuit, including its processor, is then powered-up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.