Multiple configuration data path architecture for a disk array controller
US5345565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1991 |
| Grant date | Sep 6, 1994 |
| Priority date | — |
| Expiry date | Mar 13, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disk array controller including a data path architecture which can be configured to perform data transfer operations between a host system and a plurality of disk drives configured as a RAID level 1, 3, 4 of 5 disk array. The data path architecture includes a plurality of array channels for coupling selected disk drives with a host system bus and circuitry for generating parity information during write operations. Each array channel includes a data bus connected through bus drivers to the host bus, its associated disk drive, and the input and output of the parity generation circuitry. The bus drivers control the placement of data unto the array busses and the direction of the data flow on the array busses. In addition to performing data transfer operations and generating parity information the data path architecture can be configured to check parity information, recover lost data, reconstruct disk drives, monitor data transfer operations, verify data transfer operations and broadcast information to several disk drives.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.