Method of bonding silicon and III-V semiconductor materials
US5346848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 1993 |
| Grant date | Sep 13, 1994 |
| Priority date | — |
| Expiry date | Jun 1, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon wafer and a III-V semiconductor wafer are bonded together through a bonding interlayer which is deposited on the III-V semiconductor wafer. By forming the bonding interlayer on the III-V semiconductor wafer, rather than the silicon wafer, the bonding process is facilitated, creating a sufficiently strong bond to carry out further processing. The III-V semiconductor wafer is thinned to relieve stress after the bonding procedure. The bonded wafers may be subjected to a second bonding procedure to increase the bond strength. The bonded wafers can then be subjected to high temperature processing used in semiconductor device fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.