System for interconnecting VLSI circuits with transmission line characteristics
US5347177A · kind A · utility
Inventor
Key dates
| Filing date | Jan 14, 1993 |
| Grant date | Sep 13, 1994 |
| Priority date | — |
| Expiry date | Jan 14, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
This invention provides a means to interconnect high performance CMOS VLSI circuits. LTL (a coined descriptor for describing a novel CMOS interface standard) offers improved performance by providing active threshold control of an input buffer to speed signal capture, and by controlling performance limiting characteristics of signal reflection, ground bounce, receiver overdriving and ringing. These performance limiting characteristics are controlled by providing: level-sensitive impedance control of an output driver, distributed active line termination using impedances of input buffers on a transmission line, and balanced loading using closed-loop transmission lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.