Protection structure against latch-up in a CMOS circuit

US5347185A · kind A · utility

Assignee

• SGS-Thomson Microelectronics S.A. · IT

Inventor

• François Tailliet · Gardanne, FR

Key dates

• Filing date: Jun 3, 1992
• Grant date: Sep 13, 1994
• Expiry date: Jun 3, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/601

Abstract

A CMOS circuit protected against latch-up. A limiter parallel to the internal circuitry of the CMOS circuit increases the external current for the triggering of the latch-up in the event of overvoltage on the supply. In one embodiment, the parallel limiter is intrinsically protected against electrostatic discharges. In another embodiment, the limiter is protected by a series connected resistor and a separate shunt-connected ESD protection structure.