Processor-based smart packet memory interface
US5347514A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1993 |
| Grant date | Sep 13, 1994 |
| Priority date | — |
| Expiry date | Mar 26, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processor-based packet memory interface for controlling the transfer of data between multiple communications channels and packet memory in a communications adapter is presented, where the communications adapter uses requestor IDs to identify transmit and receive processes. The processor-based packet memory interface is controlled by a microprocessor configured to perform read and write operations with the communications adapter. The microprocessor is further configured to reserve a plurality of blocks of memory in the packet memory so that the number of communications channels that can be supported is not limited to the number of requestor ID's that can be handled by the communications adapter. The processor-based packet memory interface also includes RAM, for use by the microprocessor, to store pointers to reserved blocks of memory in the packet memory and to temporarily store packet data for transfer between the communications channels and the communications adapter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.