Wafer-scale semiconductor integrated circuit device and method of forming interconnection lines arranged between chips of wafer-scale semiconductor integrated circuit device

US5349219A · kind A · utility

Assignees

• FUJITSU LIMITED · JP
• Fujitsu VLSI Limited · JP

Inventors

• Toshiaki Murao · Kawasaki, JP
• Takeo Kikuchi · Chofu, JP
• Toshihiko Iryu · Kawasaki, JP
• Hidenori Nomura · Osaka, JP
• Hiroyuki Sugamoto · Kasugai, JP

Key dates

• Filing date: Dec 30, 1993
• Grant date: Sep 20, 1994
• Expiry date: Dec 30, 2013

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A wafer-scale semiconductor integrated circuit device includes a wafer, a plurality of chips formed on the wafer, each of the chips having an internal logic circuit, interconnection lines mutually connecting the chips, and clamping circuits which are coupled to chips from among the chips which are located at a periphery of an arrangement of the chips and which prevent the interconnection lines related to the chips located at the periphery from being in a floating state.