Interrupt control system for microprocessor for handling a plurality of maskable interrupt requests
US5349667A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 1992 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Sep 8, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer includes a maskable interrupt request terminal, a maskable interrupt request terminal, and a nonmaskable interrupt request terminal, and internally contains a status register having a group of flags indicating a maskable interrupt allowing level, a flag indicating that a nonmaskable interrupt processing is under execution, a flag indicating that an exception processing is under execution, and a flag indicating inhibition of the maskable interrupt. There are also internally provided first and second save registers for saving the content of the status register and the content of a program counter, respectively, when the maskable interrupt request is acknowledged, and third and fourth save registers for saving the content of the status register and the content of a program counter, respectively, when the nonmaskable interrupt request is acknowledged. A register is provided to independently indicate the acknowledgement of the maskable interrupt and the acknowledgement of the nonmaskable interrupt, and a comparator compares the level designated by the maskable interrupt allowing level indicating flag group with an interrupt request level notified through the maskable int…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.