Apparatus for calculating delay when executing vector tailgating instructions and using delay to facilitate simultaneous reading of operands from and writing of results to same vector register
US5349677A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1991 |
| Grant date | Sep 20, 1994 |
| Priority date | — |
| Expiry date | Apr 10, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improved performance is obtained in computers of the type having vector registers which communicate with one or more functional units and common memory. As elements of a vector are read from a vector register for transmission to common memory or as operands to a functional unit, the vector register immediately becomes available to receive and store elements of a vector from common memory or a functional unit. The element-by-element storing takes place simultaneously with the element-by-element reading, and trails the reading by at least one element so as to not overwrite elements yet to be read. Through the use of this technique a vector register can be loaded with a vector for a subsequent operation without having to wait for the completion of the previous operation which uses the same vector register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.