Ferroelectric memory cell arrangement having a split capacitor plate structure
US5350705A · kind A · utility
103Cited by
11References
44Claims
0Family size
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Key dates
| Filing date | Aug 25, 1992 |
| Grant date | Sep 27, 1994 |
| Priority date | — |
| Expiry date | Aug 25, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
A ferroelectric memory cell architecture in which a pair of cells is fabricated so as to share common elements, and wherein ferroelectric capacitors are fabricated overlying the associated select transistors, thereby achieving a small-area cell architecture. First level refractory metal interconnects formed prior to ferroelectric material deposition steps are utilized with subsequently formed second metallization layers to provide interconnections between the ferroelectric capacitor plates and the underlying transistor regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.