Content addressable memory
US5351208A · kind A · utility
33Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 27, 1992 |
| Grant date | Sep 27, 1994 |
| Priority date | — |
| Expiry date | Apr 27, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory is provided that includes a memory cell and a first plurality of lines connected directly to the gates of access transistors to this memory cell. These access transistors are further connected to a second plurality of lines. The first and second plurality of lines each perform different functions during read, write, and comparison modes. In another embodiment of the present invention, p-channel transistors are used for a match transistor and its associated pass transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.