Intermittenceless switching system
US5353281A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 29, 1992 |
| Grant date | Oct 4, 1994 |
| Priority date | — |
| Expiry date | May 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An intermittenceless switching system includes two speech path memories having sufficient capacity to store a single frame of data having a plurality of time slots. The incoming data is stored in one memory, while the outgoing data is read from the other memory. A control circuit continuously alternates the read/write functions between the two memories. A control memory is used to store switch control information. The system includes a buffer memory that is present between a data processor and the control memory to prevent switch operation during data transmission. The system also includes a monitoring circuit for detecting an indication bit signifying the presence or absence of data in the time slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.