Equalizer-based timing recovery
US5353312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1991 |
| Grant date | Oct 4, 1994 |
| Priority date | — |
| Expiry date | Dec 27, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/027
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Timing recovery circuitry for recovering digital data generates a timing signal which is a function of the delay provided by an equalizer to one or more predetermined frequency components of its input signal. Advantageously, this approach is applicable to systems which utilize one or more baseband or passband equalizers. The disclosed embodiments of the present invention pertain to a dual-duplex system. In such a system, the digital data to be transmitted is divided into two different digital signals and each signal is coupled through an associated transmission channel. At the receiver, the received version of each transmitted signal is processed by an associated equalizer and the outputs therefrom are combined to recover the digital data. In the disclosed embodiments of the present invention, the necessary timing signal for such recovery is a function of the delay introduced by each equalizer to at least one predetermined frequency component of that equalizer's input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.