CPU lock logic for corrected operation with a posted write array
US5353416A · kind A · utility
20Cited by
12References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 1992 |
| Grant date | Oct 4, 1994 |
| Priority date | — |
| Expiry date | Dec 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared bus arbitration system is disclosed which provides logic allowing multiple processors to co-exist on a common bus. In the present invention, the host processor is isolated from the bus by a posted write array or write buffer. The arbitration system accepts bus lock and cycle signals when the processor writes a locked instruction to the posted write array and provides a bus lock signal to the bus when the locked instructions are written to the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.