Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller
US5353429A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1993 |
| Grant date | Oct 4, 1994 |
| Priority date | — |
| Expiry date | Aug 20, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system where a cache miss is fielded with a retry access to main memory, but instead of waiting for the microprocessor to resynchronize and re-initiate the memory cycle, the memory cycle is started immediately. The speed of the tag array is specified so that the status of the cache, hit or miss, is known at the same time that the microprocessor's memory cycle start signal is known to be valid. The addresses are then latched and the memory cycle is started in anticipation of the retried cycle. The access time of memory is then overlapped with microprocessor resynchronization and memory cycle reinitialization. By using this technique, clock cycles are needed for the initial cycle, additional clock cycles are needed to perform the resynchronization, and additional clock cycles are needed for the retried cycle since the data is already waiting from memory. The above-described improvement is implemented by decoupling the direct connection of the memory array from the address bus. Additionally, a state machine modifies the operation of the memory controller so that the access time of the memory is overlapped with microprocessor resynchronization and memory cycle reinitialization…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.