Memory address decoder with storage for memory attribute information
US5353431A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1994 |
| Grant date | Oct 4, 1994 |
| Priority date | — |
| Expiry date | Feb 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable and testable memory address decoder for a computer system where a static random access memory device is used to store memory configuration information. The computer system includes a processor which is coupled to the memory address decoder via data and address lines. The memory address decoder includes an SRAM for storing a memory map which associates memory attributes with memory ranges or blocks of memory. The memory attributes include: memory residence, caching, write protection of memory ranges, and the decoding of other memory modules. The present invention also includes control logic, a read-back register, and a mode register for controlling the loading and read back verification of the SRAM. The control logic operates the memory address decoder in one of four modes. These modes include: 1) power-up mode, 2) programming mode, 3) read back mode, and 4) normal operation mode. One of these modes is selected by loading the mode register with a value corresponding to the desired mode. A default power up mode is entered after power is first applied to the computer system. When the processor specifies a programming mode, the processor may write data directly into the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.