Method of manufacturing semiconductor integrated circuit device
US5354699A · kind A · utility
26Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1992 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Oct 22, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/009
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.