TTL to CMOS translator circuit and method
US5355032A · kind A · utility
7Cited by
7References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1993 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Mar 24, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/017518
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed, low powered, BiCMOS TTL to CMOS translator circuit and method which relies on an internally generated reference voltage and which is capable of driving high loads. The translator circuit includes a first inverting and translating stage having a pull up transistor and a pull down transistor, a high gain stage and a second inverting stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.