Static timing verification
US5355321A · kind A · utility
32Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1992 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Jun 12, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for static analysis of a software model of a circuit clocked by two clocks where the two clocks' periods are multiples of a greatest common divisor period. In the invention, a composite clock is determined with a period equal to the least common multiple of the periods of the two clocks, and the model is statically analyzed relative to the composite clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.