Arrangement of redundant cell array for semiconductor memory device
US5355337A · kind A · utility
8Cited by
8References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 13, 1992 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Apr 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device having a normal memory cell array which includes repeating arrangements of a predetermined data arrangement and whose data is input and output in response to a column select line signal, an arrangement of a redundant cell array is disclosed. The arrangement has the same data arrangement as the minimally repeated unit of said normal memory cell array, wherein the data is in the redundant cell array input and output in response to a redundant column select line signal. According to the arrangement of the redundant cell array, the reliability and yield of the semiconductor memory device are enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.