Word line selection circuit for simultaneously selecting a plurality of memory cells
US5355346A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1993 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Jul 1, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the second decode line group and the second input terminal for selecting the second decode lines in response to the second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.