High-speed integrated circuit testing with JTAG
US5355369A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1991 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Apr 26, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The use of the JTAG port provides for boundary scan testing of integrated circuits, thereby allowing for the testing of IC's after they have been mounted into a circuit board. However, the conventional JTAG scheme is limited as to speed, since both the input and output vectors must be serially shifted in and out of I/O buffers along the chip boundaries. The present invention speeds the testing of high-speed core logic circuitry by transferring the test program to a special test data register, which downloads the program to the logic circuitry under test, and uploads the results. This allows the core logic to perform the test at its normal operating speed, while still retaining compatibility with the JTAG standard for other tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.