System for compiling parallel communications instructions including their embedded data transfer information
US5355492A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1991 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Nov 5, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/45
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed towards a compiler for processing parallel communication instructions on a data parallel computer. The compiler of the present invention comprises a front end, a middle end, an optimizer, and a back end. The front end constructs a parse tree which includes nodes representative of parallel communication instructions. The middle end generates an intermediate representation (IR) tree from the parse tree. The IR tree includes general parallel communication IR nodes representative of target code to carry out parallel communication with general communication. An efficient parallel communication module of the optimizer replaces general parallel communication IR nodes with grid parallel communication IR nodes where doing so would result in more efficient target code. The grid parallel communication IR nodes represent target code to carry out parallel communication instructions with grid communication. The back end generates target code from the optimized IR tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.