Self-synchronizing data queues
US5355504A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 1991 |
| Grant date | Oct 11, 1994 |
| Priority date | — |
| Expiry date | Nov 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for enabling processor cells in a high speed multi-processor environment to communicate with each other so as to resolve synchronization problems caused by propagation and other delays inherent in such an environment. The invention is for systems for which the data delay is both bounded and fixed wherein the maximum data delay is part of the system specifications and all cells operate at the same frequency. Data is transmitted along with a clock to allow the receiving cell to properly recover the data regardless of the state of the receiver's internal clocks. Both the transmitting cell and the receiving cell are operating at the same frequency (because their clock signals are derived from the same master oscillator), but the range of delays associated with the transmission of data places no bounds on the allowable phase difference between the received data's clock and the receiver's internal clock state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.