Semiconductor storage system including defective bit replacement
US5357473A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1993 |
| Grant date | Oct 18, 1994 |
| Priority date | — |
| Expiry date | Oct 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage system comprises a semiconductor storage element array including a plurality of semiconductor memory elements, a data bus for transferring data to said semiconductor storage element array, an address bus for inputting an address to said semiconductor storage element array, a read/write controller for controlling read/write of the data written to said semiconductor storage element array, an interface control module for controlling a transfer/receipt of data and commands to and from an outside system, a microprocessor for controlling said read/write controller and said interface control module, a defect address memory for storing and outputting information on an address where at least one defective bit exists and an alternate address to be substituted for said address, and a defect address manipulating circuit for substituting said alternate address for said address where said defective bit exists in accordance with an output of said defect address memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.