Dynamic random access memory device having precharge circuit for intermittently and selectively charging data line pairs
US5357474A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1993 |
| Grant date | Oct 18, 1994 |
| Priority date | — |
| Expiry date | Oct 18, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises read-out circuits responsive to first column address decoded signals for transferring data bits from selected bit lines to data line pairs, selector circuits responsive to second column address decoded signals for transferring a data bit from selected one of the data line pairs to a read data amplifier circuit and a precharge circuit coupled between a source of power voltage level and the data line pairs for charging the selected data line pair before transmission of the data bit to the selected data line pair, and the precharge circuit isolates the data line pair from the source of power voltage level so that potential difference indicative of the data bit rapidly takes place on the selected data line pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.