Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5357617A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1991 |
| Grant date | Oct 18, 1994 |
| Priority date | — |
| Expiry date | Nov 22, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid pipelined processor and associated processing methods are described for separately handling substantially concurrently in a time division manner multiple program instruction threads. The hybrid architecture includes an instruction fetch unit, an instruction decode unit and an execution unit. The execution unit includes multiple sets of register files each of which contains the working contents for a corresponding one of a plurality n of instruction threads. Timing and control circuitry is coupled to each of the principal processor components for controlling the timing and sequence of operations on instructions from the plurality n of instruction threads such that multiple instruction threads are separately handled substantially concurrently. Corresponding hybrid processing methods for such a single pipelined processor are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.