Paged memory scheme
US5357619A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1992 |
| Grant date | Oct 18, 1994 |
| Priority date | — |
| Expiry date | Jan 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for supplying an address and data to an external memory device. The number of pins available for supplying the address is less than the number of address lines required at the external memory device. A register is used to store the high order bits of the address and is pre-loaded with a default page value. An output of the register is coupled to an address input of the external memory. If the high order bits of the address are equal to the default page value, a control device couples the data lines directly to the external memory device and a read or write operation follows. If the two values are different, a paging cycle is performed where the high order address bits are latched through the register to the address input of the external memory and then the data bits are coupled to the external memory device. If the default page value points to the most accessed portion of the external memory device, no paging is performed during access to that portion of the external memory and processing time is saved when reads or writes of data are made to that portion of the external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.