Method of manufacturing semiconductor devices
US5358621A · kind A · utility
134Cited by
1References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1992 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Nov 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device having multi-layer lead conductors, lead conductors of each layer and through connections are generated by electro chemical plating process. A flat and smooth surface is provided for each layer on which lead conductor base patterns are formed. Plating lead conductors on a layer and plating through connections are executed in a separate process. And, in these platings, electrolytic current is so controlled that the growth of plating is always from the base of the plating.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.