Silicon substrate having YSZ epitaxial barrier layer and an epitaxial superconducting layer
US5358925A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1992 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Aug 10, 2012 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC30B29/225
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
An HTSC material epitaxially deposited on a YSZ buffer layer on a surface of a monocrystalline silicon substrate has a zero resistance transition temperature of at least 85.degree. K., a transition width (10-90%) of no more than 1.0.degree. K., a resistivity at 300.degree. K. of no more than 300 micro-ohms-centimeter and a resistivity ratio (at 300.degree. K./100.degree. K.) of 3.0.+-. 0.2. The surface of the silicon substrate is cleaned using a spin-etch process to produce an atomically clean surface terminated with an atomic layer of an element such as hydrogen with does not react with silicon. The substrate can be moved to a deposition chamber without contamination. The hydrogen is evaporated in the chamber, and then YSZ is epitaxially deposited preferably by laser ablation. Thereafter, the HTSC material, such as YBCO, is epitaxially deposited preferably by laser ablation. The structure is then cooled in an atmosphere of oxygen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.