Reset monitor for detection of power failure and external reset
US5359233A · kind A · utility
14Cited by
11References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1990 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Sep 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Reset monitor for detection of power failure and external reset for devices such as microprocessors with the reset monitor providing a single settling time hold down of a reset signal. Preferred embodiments include bandgap reference with high current side compensating resistor, bond out options for analog parameter selection, glitch free state machine control of both detections, and external pushbutton debouncing both depression and release.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.