Vertical deflection with vertical shrink mode
US5359267A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 1993 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Sep 3, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N3/22
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A differential amplifier formed by a pair of transistors couples a vertical sawtooth signal to an input side of a vertical deflection amplifier. Nonlinearity of the transistor pair provides S-correction in the vertical direction. The current in the transistor pair varies when vertical height is adjusted, in service operation, so that the nonlinearity changes. In a vertical shrink mode of operation, the amplitude of the sawtooth signal is reduced. The nonlinearity associated with a given level of the sawtooth signal that corresponds to a given vertical position in the vertical shrink mode is the same as that associated with the same level of the sawtooth signal in the vertical, non-shrink mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.