Semiconductor memory device
US5359561A · kind A · utility
18Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1992 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Apr 23, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.