Memory system with adaptable redundancy
US5359563A · kind A · utility
3Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1992 |
| Grant date | Oct 25, 1994 |
| Priority date | — |
| Expiry date | Mar 9, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system with adaptable redundancy comprises address decoding means (200) for the selection of one of the rows R.sub.1 to R.sub.2 (n+1) in the memory array, according to the binary value of address A.sub.0, A.sub.1, . . . A.sub.nn incoming on bus 102. Block 200 comprises 2.sup.(n+1) blocks 201 being able to drive an activation signal on leads R.sub.1 to R.sub.2 (n+1), and having an output connected to a lead 206. Block 205 is able to drive an activation signal on lead RR according to signals present on leads 107 and 206, so as to select redundant row RR.sub.1 without the use of a redundant address decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.